The present invention relates to semiconductor devices and more specifically, to a method for improving the electromigration characteristics of patterned metal features in semiconductor devices.
Conventional semiconductor devices comprise a substrate and a plurality of interleaved dielectric and conductive layers comprising circuit patterns electrically connected by a conductive interconnection pattern metal. When metal interconnections in a semiconductor device are operated at relatively high current densities, the phenomenon of electromigration occurs which can lead to the failure of the semiconductor device. In the context of semiconductor devices, electromigration includes the movement of metal ions under the influence of electrical current and mechanical stress. Collisions between electrons and metal ions transfer momentum to the metal ions, causing the metal ions to move in the direction of current flow, which is usually toward the positive terminal. Also, patterned metal features that are operated high currents, or at a temperature relatively close to their melting points, are particularly susceptible to electromigration.
In semiconductor devices, electromigration in metal connections, such as aluminum or an alloy thereof collectively referred to hereinafter as Al, typically causes three types of failures. First, electromigration can cause metal ions to pile up in regions of an Al connection to form what are commonly referred to as xe2x80x9chillocksxe2x80x9d causing shorts between adjacent patterned metal features. Second, electromigration can cause metal ion voids in regions of an Al connection thereby increasing resistance and, in extreme circumstances, can cause opens circuits in the Al connection. Finally, electromigration can form etch pits in contacts to silicon where electrons leave silicon and enter Al.
Several techniques have been used to minimize electromigration in patterned metal features. One such technique involves adding impurities, such as copper (Cu) or titanium (Ti), to modify the properties of the patterned metal features at the grain boundaries. Typical impurity levels for Cu range from 0.5 to 4.0%. Although this technique can reduce electromigration, the added impurities tend to increase the resistance of the patterned metal features, thereby adversely affecting circuit performance. Moreover, patterned metal features containing added impurities can be more difficult to etch. For example, Alxe2x80x94Cu alloys become harder to dry etch as the Cu content is increased.
Another prior technique for minimizing electromigration involves forming a barrier layer, typically made of Ti, between a patterned metal feature and the underlying dielectric. In addition, a top cap layer, typically referred to as an anti-reflective coating, has been formed on the patterned metal feature.
Referring to FIG. 1, a conventional patterned metal feature structure, such as a metal line, is designated by the reference numeral 100. A dielectric layer 102, typically made from silicon dioxide (SiO2), is formed on a substrate 104, typically silicon (Si).
A barrier layer 106, typically made of Ti, is formed on top of dielectric layer 102. A primary conductive layer 108, such as Al, is formed on barrier layer 106. Finally, an anti-reflective coating 110, such as TiN is formed on metal line 108.
The use of barrier layer 106 and anti-reflective coating 110 tends to reduce electromigration in metal line 108, particularly vertical electromigration through a via, albeit at the cost of increasing the sheet resistance of metal layer 108. Anti-reflective coating 110 can also act as an etch stop layer.
Conventional practices also comprise annealing barrier layer 106 and anti-reflective coating 110 to diffuse Ti into the Al metal layer 108 to form TiAl3 at interfaces 112 and 114, to further reduce electromigration. However, this conventional technique further increases the sheet resistance of metal line 108.
Accordingly, there is a need for semiconductor devices exhibiting reduced electromigration failures. There is a particular need for methodology and semiconductor devices comprising patterned metal features exhibiting reduced electromigration.
An object of the present invention is a semiconductor device comprising patterned metal features exhibiting reduced electromigration.
Another object of the present invention is a method of manufacturing a semiconductor device exhibiting reduced electromigration.
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According the present invention, the foregoing and other objects are achieved in part by a semiconductor device comprising a substrate, a dielectric layer formed on the substrate, a patterned metal feature formed on the dielectric layer, wherein the patterned metal feature has a top surface, a bottom surface and side surfaces, and a conductive layer formed on at least the side surfaces of the patterned metal feature.
In another aspect of the present invention, a portion of the conductive layer is removed to provide one or more conductive sidewall spacers on the side surfaces of the patterned metal feature. Embodiments include conductive sidewall spacers formed from two layers of conductive material, such as a first layer of Ti and a second layer of titanium-nitride.
Another aspect of the invention is a method of manufacturing a semiconductor device which method comprises providing a substrate, forming a dielectric layer on the substrate, forming a patterned metal feature on the dielectric layer, wherein the patterned metal feature has a top surface, a bottom surface and side surfaces, and forming a conductive layer on at least the side surfaces of the patterned metal feature.